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[USB develop] usb_doc

Description: USB IP core.very good
Platform: | Size: 143009 | Author: 张卫 | Hits:

[USB develop] USB2.0_rtl_ipcore_verilog

Description: 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
Platform: | Size: 62383 | Author: 王椿棠 | Hits:

[USB develop] USB2.0_rtl_ipcore_verilog

Description:
Platform: | Size: 62464 | Author: 王椿棠 | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[VHDL-FPGA-Verilog] USB_2-0_Host_IP_Core

Description: this come from alter ,you can look and find it on line about USB
Platform: | Size: 89088 | Author: fff | Hits:

[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[USB develop] USBipcore

Description: usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
Platform: | Size: 155648 | Author: liu | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] 1

Description: 15个免费的IP核 usb11,i2c,pci_core,video_compression_systems等等.-15 free IP core usb11, i2c, pci_core, video_compression_systems and so on.
Platform: | Size: 2646016 | Author: likufan | Hits:

[VHDL-FPGA-Verilog] usb_latest.tar

Description: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Platform: | Size: 196608 | Author: liang | Hits:

[Embeded-SCM Develop] Usb_ISP1362

Description: 飞利浦公司Usb芯片ISP1362在nios中的IP核，可以用-Philips Usb-chip ISP1362 in nios in the IP core, you can use
Platform: | Size: 18432 | Author: KKK | Hits:

[Embeded-SCM Develop] usb20_ipcore_usb_funct

Description: usb 2.0协议的ip核，可用，里面程序有文档说明-usb 2.0 protocol ip core, can be used, which procedures are documented
Platform: | Size: 208896 | Author: KKK | Hits:

[USB develop] ISP1362-IP

Description: ISP1362的IP核用在USB 控制上可与PC通讯，作为SOPC的IP核-ISP1362' s USB IP core used in the control of communication with PC as the IP core SOPC
Platform: | Size: 18432 | Author: 赵擎天 | Hits:

[Embeded Linux] linux_transplantation

Description: 《S3C44B0开发板移植内核2.6 uclinux记录》以及一篇论文《基于Linux的USB 2.0 OTG IP核主机驱动的研究与实现》。-" S3C44B0 development board transplantation kernel 2.6 uclinux record" and a paper " Linux-based USB 2.0 OTG IP core host-driven research and implementation."
Platform: | Size: 5438464 | Author: zz | Hits:

[VHDL-FPGA-Verilog] USB_Verilog_IP

Description: USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
Platform: | Size: 143360 | Author: xsp | Hits:

[VHDL-FPGA-Verilog] USB2.0-IP

Description: USB2.0 IP核源代码，经典好用！写这么多真没意思！-USB 2.0 IP core source code, easy to use classic! Write so really boring!
Platform: | Size: 229376 | Author: sulianghe | Hits:

[Linux-Unix] be_ethtool

Description: register bits of the ChipIdea USB IP core for Embedded Linux.
Platform: | Size: 8192 | Author: bivaiha | Hits:

[Linux-Unix] otg

Description: ChipIdea USB IP core OTG driver for Embedded Linux.
Platform: | Size: 2048 | Author: seizingxun | Hits:

[Linux-Unix] cuboot-rainier

Description: MIPS USB IP core family device controller.
Platform: | Size: 2048 | Author: gounsws | Hits:

[USB develop] USB-IPcore-Verilog

Description: USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
Platform: | Size: 5345280 | Author: 赵海峰 | Hits:
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